Roadmap on ferroelectric hafnia- and zirconia-based materials and devices

Ferroelectric hafnium and zirconium oxides have undergone rapid scientific development over the last decade, pushing them to the forefront of ultralow-power electronic systems. Maximizing the potential application in memory devices or supercapacitors of these materials requires a combined effort by the scientific community to address technical limitations, which still hinder their application. Besides their favorable intrinsic material properties, HfO2–ZrO2 materials face challenges regarding their endurance, retention, wake-up effect, and high switching voltages. In this Roadmap, we intend to combine the expertise of chemistry, physics, material, and device engineers from leading experts in the ferroelectrics research community to set the direction of travel for these binary ferroelectric oxides. Here, we present a comprehensive overview of the current state of the art and offer readers an informed perspective of where this field is heading, what challenges need to be addressed, and possible applications and prospects for further development

A Novel Compact Circuit for 4-PAM Energy-Efficient High Speed Interconnect Data Transmission and Reception

Abstract--Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50 % improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise-margin. Index Terms—Multi-valued logic, pulse amplitude modulation, back-gate bias, fully-depleted SOI, low-power, global interconnect delay, circuit optimization.